This invention relates to semiconductor devices, and more particularly to circuits for rapid testing of cell arrays and the like in dynamic memory devices.
Dynamic MOS read/write memory devices have been constructed generally as shown in U.S. Pat. No. 4,081,701 (a 16K dynamic RAM) issued to White, McAdams and Redwine, or U.S. Pat. No. 4,239,993 (a 64K dynamic RAM) issued to McAlexander, White and Rao, both assigned to Texas Instruments. When memory devices of this type are manufactured in higher densities, such as 256K and 1-Megabit and beyond, the problem of testing all of the cells and all of the other circuits on the chip becomes formidible.
Dynamic RAMs are tested using a large number of different test patterns which are repeated for all cells of the array, and often each test pattern requires several accesses to each cell. Thus, if the device contains 1-M cels then a complete test sequence of the conventianal type may require several hundred million accesses. The time that a given device remains on the test machine becomes a large factor in manufacturing cost.
Additional test time is required if more detailed test data is to be obtained for defect analysis, such as that described in U.S. patent application Ser. No. 604,115 filed Apr. 26, 1984, by White and Zivitz, assigned to Texas instruments. If the particular type and cause of failure is to be extracted from the test data, rather than merely a "go or no-go", pass or fail outcome, then a lot more test time is needed, beyond the standard sequence of test patterns.
It is the principal object of this invention to provide improved test methods for high density dynamic RAM devices or the like, particularly for determining specific types of failures. Another object is to provide testing circuitry for a dynamic RAM in which the testing time is minimized, yet the circuitry added to the device is minimized. A further object is to provide high speed test circuitry for semiconductor devices which contain arrays of cells and the like.